PIC18F45J10 Datasheet, PDF (105/358 Pages) Microchip Technology – 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

PIC18F45J10 FAMILY
9.5 PORTD, TRISD and LATD
Registers
Note: PORTD is only available in 40/44-pin
devices.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable as an
input or output.
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 14.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 9.7 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
Note:
When the Enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
EXAMPLE 9-5: INITIALIZING PORTD
CLRF PORTD
CLRF LATD
MOVLW 0CFh
MOVWF TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 103