PIC18F4321 Datasheet, PDF (88/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
7.5 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
7.6 Protection Against Spurious Write
To protect against spurious EEPROM writes, various
mechanisms have been implemented. On power-up,
the WREN bit is cleared. In addition, writes to the
EEPROM are blocked during the Power-up Timer
period (TPWRT, parameter 33).
The write initiate sequence and the WREN bit together
help prevent an accidental write during Brown-out
Reset, power glitch or software malfunction.
7.7 Using the Data EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing data. Such data is
typically updated at least one time within the number of
writes defined by specification D124. If any location
storing data is not written at least this often, the data
EEPROM array must be refreshed. For this reason,
values that change infrequently, or not at all, should be
stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
If data EEPROM is used to store either:
1) only constants (i.e., data that is
infrequently or never changed),
or
2) only frequently changing data, then an
array refresh is likely not required but
should be verified by the user. If a mix-
ture of these types of data are being
stored, it is the responsibility of the
user to determine when an array
refresh is required.
EXAMPLE 7-3:
Loop
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
DATA EEPROM REFRESH ROUTINE
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
BCF
EECON1, WREN
BSF
INTCON, GIE
; Disable writes
; Enable interrupts
DS39689E-page 86
Preliminary
© 2007 Microchip Technology Inc.