PIC18F4321 Datasheet, PDF (14/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
SPDIP,
Pin Buffer
SOIC, QFN ^{Type Type}
SSOP
Description
MCLR/VPP/RE3
MCLR
VPP
RE3
1
26
Master Clear (input) or programming voltage (input).
I ST Master Clear (Reset) input. This pin is an active-low
Reset to the device.
P
Programming voltage input.
I ST Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
9
6
Oscillator crystal or external clock input.
I Analog Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
I Analog External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I/O TTL General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10
7
Oscillator crystal or clock output.
O—
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
O—
In RC, EC and INTIO modes, OSC2 pin outputs CLKO
which has one-fourth the frequency of OSC1 and denotes
the instruction cycle rate.
I/O TTL General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I²C = ST with I²C™ or SMB levels
CMOS = CMOS compatible input or output
I
= Input
P = Power
O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39689E-page 12
Preliminary
© 2007 Microchip Technology Inc.