PIC18F4321 Datasheet, PDF (52/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
2221 2321 4221 4321
---- 0000
---- 0000
---- uuuu
FSR1L
2221 2321 4221 4321
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
2221 2321 4221 4321
---- 0000
---- 0000
---- uuuu
INDF2
2221 2321 4221 4321
N/A
N/A
N/A
POSTINC2 2221 2321 4221 4321
N/A
N/A
N/A
POSTDEC2 2221 2321 4221 4321
N/A
N/A
N/A
PREINC2
2221 2321 4221 4321
N/A
N/A
N/A
PLUSW2
2221 2321 4221 4321
N/A
N/A
N/A
FSR2H
2221 2321 4221 4321
---- 0000
---- 0000
---- uuuu
FSR2L
2221 2321 4221 4321
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
2221 2321 4221 4321
---x xxxx
---u uuuu
---u uuuu
TMR0H
2221 2321 4221 4321
0000 0000
0000 0000
uuuu uuuu
TMR0L
2221 2321 4221 4321
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
2221 2321 4221 4321
1111 1111
1111 1111
uuuu uuuu
OSCCON
2221 2321 4221 4321
0100 q000
0100 q000
uuuu uuqu
HLVDCON 2221 2321 4221 4321
0-00 0101
0-00 0101
u-uu uuuu
WDTCON
RCON⁽⁴⁾
2221 2321 4221 4321
2221 2321 4221 4321
---- ---0
0q-1 11q0
---- ---0
0q-q qquu
---- ---u
uq-u qquu
TMR1H
2221 2321 4221 4321
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
2221 2321 4221 4321
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
2221 2321 4221 4321
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
2221 2321 4221 4321
0000 0000
0000 0000
uuuu uuuu
PR2
2221 2321 4221 4321
1111 1111
1111 1111
1111 1111
T2CON
2221 2321 4221 4321
-000 0000
-000 0000
-uuu uuuu
SSPBUF
2221 2321 4221 4321
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
2221 2321 4221 4321
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
2221 2321 4221 4321
0000 0000
0000 0000
uuuu uuuu
SSPCON1 2221 2321 4221 4321
0000 0000
0000 0000
uuuu uuuu
SSPCON2 2221 2321 4221 4321
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
DS39689E-page 50
Preliminary
© 2007 Microchip Technology Inc.