PIC18F4321 Datasheet, PDF (221/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
FIGURE 18-6:
EUSART RECEIVE BLOCK DIAGRAM
BRG16
x64 Baud Rate CLK
SPBRGH SPBRG
Baud Rate Generator
CREN
÷ 64
or
÷ 16
or
÷4
OERR
FERR
MSb
Stop ₍₈₎
RSR Register
7 ••• 1
LSb
0 Start
Pin Buffer
and Control
Data
Recovery
RX
RXDTP
SPEN
Interrupt
RX9
RX9D
RCREG Register
FIFO
RCIF
RCIE
8
Data Bus
FIGURE 18-7:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
ASYNCHRONOUS RECEPTION, TXCKP = 0 (TX NOT INVERTED)
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Start
bit 7/8 Stop bit
bit
bit 7/8 ^Stop
bit
Word 1
RCREG
Word 2
RCREG
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing
the OERR (overrun) bit to be set.
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
49
PIR1
PSPIF⁽¹⁾
ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1
PSPIE⁽¹⁾ ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1
PSPIP⁽¹⁾ ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
51
RCREG EUSART Receive Register
51
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
51
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
51
SPBRGH EUSART Baud Rate Generator Register High Byte
51
SPBRG
EUSART Baud Rate Generator Register Low Byte
51
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39689E-page 219