PIC18F4321 Datasheet, PDF (260/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
REGISTER 23-5:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
R/P-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
DEBUG XINST BBSIZ1 BBSIZ0 ICPORT⁽¹⁾ LVP
—
STVREN
bit 7
bit 0
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
BBSIZ1:BBSIZ0: Boot Block Size Select bits
PIC18F4221/4321 Devices:
1x = 1024 Words
01 = 512 Words
00 = 256 Words
PIC18F2221/2321 Devices:
1x = 512 Words
x1 = 512 Words
00 = 256 Words
ICPORT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit⁽¹⁾
1 = ICPORT enabled
0 = ICPORT disabled
LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Note 1: Available only on PIC18F4221/4321 devices in 44-pin TQFP packages. Always
leave this bit clear in all other devices.
Legend:
R = Readable bit
C = Clearable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS39689E-page 258
Preliminary
© 2007 Microchip Technology Inc.