PIC18F4321 Datasheet, PDF (176/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I²C™ MODE) – CONTINUED
R/W-0
GCEN
R/W-0
ACKSTAT
R/W-0
ACKDT/
ADMSK5
R/W-0 R/W-0 R/W-0 R/W-0
ACKEN⁽¹⁾/ RCEN⁽¹⁾/ PEN⁽¹⁾/ RSEN⁽¹⁾/
ADMSK4 ADMSK3 ADMSK2 ADMSK1
R/W-0
SEN⁽¹⁾
bit 7
bit 0
bit 0 SEN: Start Condition Enable/Stretch Enable bit⁽¹⁾
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is active, these bits
may not be set (no spooling) and the SSPBUF may not be written (or writes to the
SSPBUF are disabled).
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 17-6:
SSPADD: MSSP ADDRESS REGISTER⁽¹⁾
R/W-0
R/W-0
R/W-0
R/W-0
ADD7
ADD6
ADD5
ADD4
bit 7
R/W-0
ADD3
R/W-0
ADD2
R/W-0
ADD1
R/W-0
ADD0
bit 0
bit 7-0
ADD<7:0>: MSSP Address bits
Note 1: MSSP Address register in 1²C Slave mode. MSSP Baud Rate register in I²C Master
mode.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39689E-page 174
Preliminary
© 2007 Microchip Technology Inc.