PIC18F4321 Datasheet, PDF (317/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
24.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F4321 family devices also
provide an optional extension to the core CPU function-
ality. The added features include eight additional
instructions that augment indirect and indexed
addressing operations and the implementation of
Indexed Literal Offset Addressing mode for many of the
standard PIC18 instructions.
The additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST Configuration bit.
The instructions in the extended set (with the exception
of CALLW, MOVSF and MOVSS) can all be classified as
literal operations, which either manipulate the File
Select Registers, or use them for indexed addressing.
Two of the instructions, ADDFSR and SUBFSR, each
have an additional special instantiation for using FSR2.
These versions (ADDULNK and SUBULNK) allow for
automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
• software Stack Pointer manipulation
• manipulation of variables located in a software
stack
A summary of the instructions in the extended instruction
set is provided in Table 24-3. Detailed descriptions are
provided in Section 24.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 24-1
(page 274) apply to both the standard and extended
PIC18 instruction sets.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who may
be reviewing code that has been
generated by a compiler.
24.2.1 EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byte-
oriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 24.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”.
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
Mnemonic,
Operands
Description
16-Bit Instruction Word
Cycles
MSb
LSb
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
f, k
k
z_s, f_d
z_s, z_d
k
f, k
k
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
Move z_s (source) to 1st word
f_d (destination)2nd word
Move z_s (source) to 1st word
z_d (destination)2nd word
Store literal at FSR2,
decrement FSR2
Subtract literal from FSR
Subtract literal from FSR2 and
return
1
1110 1000 ffkk kkkk
2
1110 1000 11kk kkkk
2
0000 0000 0001 0100
2
1110 1011 0zzz zzzz
1111 ffff ffff ffff
2
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1
1110 1010 kkkk kkkk
1
1110 1001 ffkk kkkk
2
1110 1001 11kk kkkk
Status
Affected
None
None
None
None
None
None
None
None
© 2007 Microchip Technology Inc.
Preliminary
DS39689E-page 315