PIC18F4321 Datasheet, PDF (270/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
23.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC^® devices.
The user program memory is divided into three blocks.
One of these is a boot block of variable size. The
remainder of the memory is divided into two blocks on
binary boundaries.
Each of the three blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
FIGURE 23-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F4321 FAMILY DEVICES
MEMORY SIZE/DEVICE
Address
Range
Block Code Protection
Controlled By:
8 Kbytes
(PIC18FX321)
4 Kbytes
(PIC18FX221)
BBSIZ<1:0>
11/10
Boot Block
1K word
Block 0
1K word
01
Boot Block
512 words
Block 0
1.5K words
00
Boot Block
256 words
Block 0
1.75K words
11/10/01
Boot Block
512 words
Block 0
0.5K words
00
Boot Block
256 words
000000h
0001FFh
000200h
Block 0
0.75K words
0003FFh
000400h
0007FFh
000800h
Block 1
1K word
Block 1
1K word
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000FFFh
001000h
CP1, WRT1, EBTR1
Block 1
2K words
Block 1
2K words
Block 1
2K words
Unimplemented
Reads all ‘0’s
Unimplemented
Reads all ‘0’s
001FFFh
002000h
1FFFFFh
(Unimplemented Memory
Space)
DS39689E-page 268
Preliminary
© 2007 Microchip Technology Inc.