PIC18F4321 Datasheet, PDF (81/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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6.5 Writing to Flash Program Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 8 times
for each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. At the end of updating
the 8 holding registers, the EECON1 register must be
written to in order to start the programming operation with
a long write.
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Note:
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the modification
does not attempt to change any bit from a
‘0’ to a ‘1’. When modifying individual bytes,
it is not necessary to load all 8 holding
registers before executing a write operation.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
Holding Register
Holding Register
Holding Register
8
TBLPTR = xxxxx7
Holding Register
Program Memory
6.5.1
FLASH PROGRAM MEMORY
WRITE SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the row erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 8 bytes into the holding registers.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Repeat from step 5 seven more times.
14. Re-enable interrupts.
15. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 8 bytes in
the holding register.
© 2007 Microchip Technology Inc.
Preliminary
DS39689E-page 79