PIC18F4321 Datasheet, PDF(280/396 Page) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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PIC18F4321 Datasheet, PDF (280/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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PIC18F4321 FAMILY

TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands

Description

16-Bit Instruction Word

Cycles

MSb

LSb

Status

Affected

Notes

LITERAL OPERATIONS

ADDLW k

Add literal and WREG

1

ANDLW k

AND literal with WREG

1

IORLW k

Inclusive OR literal with WREG 1

LFSR

f, k Move literal (12-bit) 2nd word

2

to FSR(f)

1st word

MOVLB k

Move literal to BSR<3:0>

1

MOVLW k

Move literal to WREG

1

MULLW k

Multiply literal with WREG

1

RETLW k

Return with literal in WREG

2

SUBLW k

Subtract WREG from literal

1

XORLW k

Exclusive OR literal with WREG 1

0000

0000

0000

1110

1111

0000

0000

0000

0000

0000

0000

1111

1011

1001

1110

0000

0001

1110

1101

1100

1000

1010

kkkk

kkkk

kkkk

00ff

kkkk

0000

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

C, DC, Z, OV, N

Z, N

Z, N

None

None

None

None

None

C, DC, Z, OV, N

Z, N

DATA MEMORY â PROGRAM MEMORY OPERATIONS

TBLRD*

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read

2

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

2

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

1000

1001

1010

1011

1100

1101

1110

1111

None

None

None

None

None

None

None

None

Note 1:

2:

3:

4:

When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is â1â for a pin configured as input and is driven low by an

external device, the data will be written back with a â0â.

If this instruction is executed on the TMR0 register (and where applicable, âdâ = 1), the prescaler will be cleared if

assigned.

If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

DS39689E-page 278

Preliminary

Â© 2007 Microchip Technology Inc.

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