PIC18F4321 Datasheet, PDF (162/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
RCON
PIR1
PIE1
IPR1
GIE/GIEH PEIE/GIEL
IPEN SBOREN⁽¹⁾
PSPIF⁽²⁾
ADIF
PSPIE⁽²⁾
ADIE
PSPIP⁽²⁾
ADIP
TMR0IE
—
RCIF
RCIE
RCIP
INT0IE
RI
TXIF
TXIE
TXIP
RBIE
TMR0IF INT0IF
RBIF
49
TO
PD
POR
BOR
48
SSPIF CCP1IF TMR2IF TMR1IF
52
SSPIE CCP1IE TMR2IE TMR1IE
52
SSPIP CCP1IP TMR2IP TMR1IP
52
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF HLVDIF TMR3IF CCP2IF
52
PIE2
OSCFIE CMIE
—
EEIE
BCLIE HLVDIE TMR3IE CCP2IE
52
IPR2
OSCFIP CMIP
—
EEIP
BCLIP HLVDIP TMR3IP CCP2IP
52
TRISB
PORTB Data Direction Control Register
52
TRISC
PORTC Data Direction Control Register
52
TRISD⁽²⁾ PORTD Data Direction Control Register
52
TMR1L
Timer1 Register Low Byte
50
TMR1H Timer1 Register High Byte
50
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
TMR2
Timer2 Register
50
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
PR2
Timer2 Period Register
50
TMR3L
Timer3 Register Low Byte
51
TMR3H Timer3 Register High Byte
51
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
CCPR1L Capture/Compare/PWM Register 1 Low Byte
51
CCPR1H Capture/Compare/PWM Register 1 High Byte
51
CCP1CON P1M1⁽²⁾ P1M0⁽²⁾
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1⁽²⁾ PSSBD0⁽²⁾ 51
ECCP1DEL PRSEN PDC6⁽²⁾
PDC5⁽²⁾
PDC4⁽²⁾
PDC3⁽²⁾ PDC2⁽²⁾ PDC1⁽²⁾ PDC0⁽²⁾
51
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled
and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are unimplemented on 28-pin devices; always maintain these bits clear.
DS39689E-page 160
Preliminary
© 2007 Microchip Technology Inc.