PIC18F4321 Datasheet, PDF (274/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
Even when the dedicated port is enabled, the ICSP and
ICD functions remain available through the legacy port.
When VIH is seen on the MCLR/VPP/RE3 pin, the state
of the ICRST/ICVPP pin is ignored.
Note 1: The ICPORT Configuration bit can only
be programmed through the default ICSP
port.
2: The ICPORT Configuration bit must be
maintained clear for all 28-pin and 40-pin
devices; otherwise, unexpected operation
may occur.
23.9.2 28-PIN EMULATION
PIC18F4221/4321 devices in 44-pin TQFP packages
also have the ability to change their configuration under
external control for debugging purposes. This allows
the device to behave as if it were a PIC18F2221/2321
28-pin device.
This 28-pin Configuration mode is controlled through a
single pin, NC/ICPORTS. Connecting this pin to VSS
forces the device to function as a 28-pin device; fea-
tures normally associated with the 40/44-pin devices
are disabled, along with their corresponding control
registers and bits. This includes PORTD and PORTE,
the SPP and the Enhanced PWM functionality of
CCP1. On the other hand, connecting the pin to VDD
forces the device to function in its default configuration.
The configuration option is only available when back-
ground debugging and the dedicated ICD/ICSP port
are both enabled (DEBUG Configuration bit is clear
and ICPRT Configuration bit is set). When disabled,
NC/ICPORTS is a No Connect pin.
23.10 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply Program-
ming is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then
dedicated to controlling Program mode entry and is not
available as a general purpose I/O pin.
While programming, using Single-Supply Program-
ming, VDD is applied to the MCLR/VPP/RE3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: By default, Single-Supply ICSP Program-
ming is enabled in unprogrammed
devices (as supplied from Microchip) and
erased devices.
3: When Single-Supply ICSP Programming
is enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
4: When LVP is enabled, externally pull the
PGM pin to VSS to allow normal program
execution.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP/RE3 pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a block erase is required. If a block erase is to
be performed when using Single-Supply ICSP
Programming, the device must be supplied with VDD of
4.5V to 5.5V.
DS39689E-page 272
Preliminary
© 2007 Microchip Technology Inc.