PIC18F4321 Datasheet, PDF (18/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin Buffer
PDIP QFN TQFP ^{Type Type}
Description
MCLR/VPP/RE3
MCLR
VPP
RE3
1 18 18
Master Clear (input) or programming voltage (input).
I
ST
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
P
Programming voltage input.
I
ST
Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
13 32 30
Oscillator crystal or external clock input.
I Analog Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode;
analog otherwise.
I Analog External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I/O TTL General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 33 31
Oscillator crystal or clock output.
O
—
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
O
—
In RC, EC and INTIO modes, OSC2 pin outputs
CLKO which has one-fourth the frequency of OSC1
and denotes the instruction cycle rate.
I/O TTL General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I²C = ST with I²C™ or SMB levels
CMOS = CMOS compatible input or output
I
= Input
P = Power
O = Output
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features
(44-Pin TQFP Packages Only)” for more information.
DS39689E-page 16
Preliminary
© 2007 Microchip Technology Inc.