PIC18F4321 Datasheet, PDF (34/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
2.8 Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the configured
oscillator continues to run without interruption. For all
other power-managed modes, the oscillator using the
OSC1 pin is disabled. The OSC1 pin (and OSC2 pin in
Crystal Oscillator modes) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features, regardless of the power-
managed mode (see Section 23.2 “Watchdog Timer
(WDT)” and Section 23.4 “Fail-Safe Clock Monitor”
for more information). The INTOSC output at 8 MHz
may be used directly to clock the device or may be
divided down by the postscaler. The INTOSC output is
disabled if the clock is provided directly from the INTRC
output. The INTOSC output is also enabled for Two-
Speed Start-up at 1 MHz after Resets and when
configured for wake from Sleep mode.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a Real-
Time Clock. Other features may be operating that do
not require a device clock source (i.e., MSSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 26.2 “DC Characteristics”.
2.9 Power-up Delays
Power-up delays are controlled by two or three timers,
so that no external Reset circuitry is required for most
applications. The delays ensure that the device is kept
in Reset until the device power supply is stable under
normal circumstances and the primary clock is operat-
ing and stable. For additional information on power-up
delays, see Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT) which
provides a fixed delay on power-up (parameter 33,
Table 26-10). It is enabled by clearing (= 0) the
PWRTEN Configuration bit (CONFIG2L<0>).
2.9.1
DELAYS FOR POWER-UP AND
RETURN TO PRIMARY CLOCK
The second timer is the Oscillator Start-up Timer
(OST), intended to delay execution until the crystal
oscillator is stable (LP, XT and HS modes). The OST
does this by counting 1024 oscillator cycles before
allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, a third
timer delays execution for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency. At the end of these delays,
the OSTS bit (OSCCON<3>) is set.
There is a delay of interval TCSD (parameter 38,
Table 26-10), once execution is allowed to start, when
the controller becomes ready to execute instructions.
This delay runs concurrently with any other delays.
This may be the only delay that occurs when any of the
EC, RC or INTIO modes are used as the primary clock
source.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode
OSC1 Pin
OSC2 Pin
RC, INTIO1
Floating, external resistor pulls high
At logic low (clock/4 output)
RCIO
Floating, external resistor pulls high
Configured as PORTA, bit 6
INTIO2
Configured as PORTA, bit 7
Configured as PORTA, bit 6
ECIO
Floating, driven by external clock
Configured as PORTA, bit 6
EC
Floating, driven by external clock
At logic low (clock/4 output)
LP, XT and HS
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39689E-page 32
Preliminary
© 2007 Microchip Technology Inc.