PIC18F4321 Datasheet, PDF (385/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Data Memory ..................................................................... 59
Access Bank .............................................................. 61
and the Extended Instruction Set ............................... 69
Bank Select Register (BSR) ....................................... 59
General Purpose Registers ........................................ 61
Map for PIC18F4321 Family ...................................... 60
Special Function Registers ........................................ 62
DAW ................................................................................. 292
DC and AC Characteristics
Graphs and Tables .................................................. 365
DC Characteristics ........................................................... 340
Power-Down and Supply Current ............................ 331
Supply Voltage ......................................................... 330
DCFSNZ .......................................................................... 293
DECF ............................................................................... 292
DECFSZ ........................................................................... 293
Dedicated ICD/ICSP Port ................................................. 271
Development Support ...................................................... 323
Device Differences ........................................................... 377
Device Overview .................................................................. 7
Details on Individual Family Members ......................... 8
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Device Reset Timers .......................................................... 45
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence .................................................... 45
Direct Addressing ............................................................... 68
E
Effect on Standard PIC Instructions ................................. 320
Effects of Power-Managed Modes on
Various Clock Sources ............................................... 32
Electrical Characteristics .................................................. 327
Enhanced Capture/Compare/PWM (ECCP) .................... 147
Associated Registers ............................................... 160
Capture and Compare Modes .................................. 148
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 148
Pin Configurations for ECCP1 ................................. 148
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 148
Timer Resources ...................................................... 148
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time ................................................ 232
A/D Minimum Charging Time ................................... 232
Errata ................................................................................... 6
EUSART
Asynchronous Mode ................................................ 215
12-Bit Break Transmit and Receive ................. 221
Associated Registers, Receive ........................ 219
Associated Registers, Transmit ....................... 217
Auto-Wake-up on Sync Break ......................... 220
Receiver ........................................................... 218
Setting up 9-Bit Mode with
Address Detect ........................................ 218
Transmitter ....................................................... 215
Baud Rate Generator
Operation in Power-Managed Mode ................ 209
PIC18F4321 FAMILY
Baud Rate Generator (BRG) ................................... 209
Associated Registers ....................................... 210
Auto-Baud Rate Detect .................................... 213
Baud Rate Error, Calculating ........................... 210
Baud Rates, Asynchronous Modes ................. 211
High Baud Rate Select (BRGH Bit) ................. 209
Sampling ......................................................... 209
Synchronous Master Mode ...................................... 222
Associated Registers, Receive ........................ 224
Associated Registers, Transmit ....................... 223
Reception ........................................................ 224
Transmission ................................................... 222
Synchronous Slave Mode ........................................ 225
Associated Registers, Receive ........................ 226
Associated Registers, Transmit ....................... 225
Reception ........................................................ 226
Transmission ................................................... 225
Extended Instruction Set
ADDFSR .................................................................. 316
ADDULNK ............................................................... 316
and Using MPLAB IDE Tools .................................. 322
CALLW .................................................................... 317
Considerations for Use ............................................ 320
MOVSF .................................................................... 317
MOVSS .................................................................... 318
PUSHL ..................................................................... 318
SUBFSR .................................................................. 319
SUBULNK ................................................................ 319
Syntax ...................................................................... 315
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ........................................... 253, 266
Exiting Operation ..................................................... 266
Interrupts in Power-Managed Modes ...................... 267
POR or Wake from Sleep ........................................ 267
WDT During Oscillator Failure ................................. 266
Fast Register Stack ........................................................... 56
Firmware Instructions ...................................................... 273
Flash Program Memory ..................................................... 73
Associated Registers ................................................. 81
Control Registers ....................................................... 74
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ........................ 76
TBLPTR (Table Pointer) Register ...................... 76
Erase Sequence ........................................................ 78
Erasing ...................................................................... 78
Operation During Code-Protect ................................. 81
Reading ..................................................................... 77
Table Pointer
Boundaries ........................................................ 76
Boundaries Based on Operation ....................... 76
Operations with TBLRD and TBLWT (table) ..... 76
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing ....................................................................... 79
Protection Against Spurious Writes ................... 81
Unexpected Termination ................................... 81
Write Verify ........................................................ 81
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 294
© 2007 Microchip Technology Inc.
Preliminary
DS39689E-page 383