PIC18F4321 Datasheet, PDF(271/396 Page) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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PIC18F4321 Datasheet, PDF (271/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

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PIC18F4321 FAMILY

TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

300008h CONFIG5L â

â

â

â

â

300009h CONFIG5H CPD

CPB

â

â

â

30000Ah CONFIG6L â

â

â

â

â

30000Bh CONFIG6H WRTD WRTB WRTC

â

â

30000Ch CONFIG7L â

â

â

â

â

30000Dh CONFIG7H â

EBTRB

â

â

â

Legend: Shaded cells are unimplemented.

Bit 2

â

â

â

â

â

â

Bit 1

CP1

â

WRT1

â

EBTR1

â

Bit 0

CP0

â

WRT0

â

EBTR0

â

23.5.1 PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

In normal execution mode, the CPn bits have no direct

effect. CPn bits inhibit external reads and writes. A

block of user memory may be protected from table

writes if the WRTn Configuration bit is â0â. The EBTRn

bits control table reads. For a block of user memory

with the EBTRn bit set to â0â, a table read instruction

that executes from within that block is allowed to read.

A table read instruction that executes from a location

outside of that block is not allowed to read and will result

in reading â0âs. Figures 23-6 through 23-8 illustrate table

write and table read protection.

Note:

Code protection bits may only be written to

a â0â from a â1â state. It is not possible to

write a â1â to a bit in the â0â state. Code

protection bits are only set to â1â by a full

chip erase or block erase function. The full

chip erase and block erase functions can

only be initiated via ICSP operation or an

external programmer.

FIGURE 23-6:

TABLE WRITE (WRTn) DISALLOWED

Register Values

Program Memory(1)

Configuration Bit Settings

Boot Block

WRTB, EBTRB = 11

TBLPTR = 0008FFh

PC = 003FFEh

PC = 00BFFEh

Block 0

TBLWT*

Block 1

TBLWT*

WRT0, EBTR0 = 01

WRT1, EBTR1 = 11

Results: All table writes disabled to Blockn whenever WRTn = 0.

Note 1: See Figure 23-5 for block boundaries.

Â© 2007 Microchip Technology Inc.

Preliminary

DS39689E-page 269

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