PIC18F4321 Datasheet, PDF (37/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
1
2
3
n-1 n
Clock Transition⁽¹⁾
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
Note 1: Clock transition typically occurs within 2-4 TOSC.
PC + 4
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4 Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
PLL Clock
Output
CPU Clock
TOST⁽¹⁾
TPLL⁽¹⁾
1 2 n-1 n
Clock
Transition⁽²⁾
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
SCS1:SCS0 bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
3.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator block
(either INTRC or INTOSC), there are no distinguishable
differences between PRI_RUN and RC_RUN modes
during execution. However, a clock switch delay will
occur during entry to and exit from RC_RUN mode.
Therefore, if the primary clock source is the internal
oscillator block, the use of RC_RUN mode is not
recommended.
This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recommended that the SCS0
bit also be cleared; this is to maintain software compat-
ibility with future devices. When the clock source is
switched to the INTOSC multiplexer (see Figure 3-3),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
Note:
Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
© 2007 Microchip Technology Inc.
Preliminary
DS39689E-page 35