PIC18F4321 Datasheet, PDF (196/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
17.4.9
I²C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I²C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins count-
ing. SDA and SCL must be sampled high for one TBRG.
This action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode, or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
17.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 17-22: REPEAT START CONDITION WAVEFORM
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
SDA = 1,
SCL = 1
S bit set by hardware
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG TBRG TBRG
SDA
1st bit
RSEN bit set by hardware
on falling edge of ninth clock,
end of Xmit
SCL
Write to SSPBUF occurs here
TBRG
TBRG
Sr = Repeated Start
DS39689E-page 194
Preliminary
© 2007 Microchip Technology Inc.