PIC18F4321 Datasheet, PDF (366/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F4321 FAMILY
FIGURE 26-23: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK⁽¹⁾
132
A/D DATA
9
8 7 ^{... ...} 2
1
0
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
TCY
DONE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
PIC18FXXXX
PIC18LFXXXX
0.7 25.0⁽¹⁾ μs TOSC based, VREF ≥ 3.0V
1.4 25.0⁽¹⁾ μs VDD = 2.0V;
TOSC based, VREF full range
PIC18FXXXX
TBD
1
μs A/D RC mode
PIC18LFXXXX
TBD
3
μs VDD = 2.0V; A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)⁽²⁾
132 TACQ Acquisition Time⁽³⁾
11
12
TAD
1.4
—
μs -40°C to +85°C
TBD
—
μs 0°C ≤ to ≤ +85°C
135 TSWC Switching Time from Convert → Sample
— (Note 4)
136 TDIS Discharge Time
0.2
—
μs
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
DS39689E-page 364
Preliminary
© 2007 Microchip Technology Inc.