IA186EM_11 Datasheet, PDF (99/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
acknowledge cycle timing. Figure 19 presents the software halt cycle. Table 89 presents the
software halt cycle timing. Figure 20 presents the clock—active mode. Figure 21 presents the
clock—power-save mode. Table 90 presents the clock timing.
Figure 22 presents the srdy—synchronous ready. Figure 23 presents the ardy—asynchronous
ready. Figure 24 presents the peripherals. Table 91 presents the ready and peripheral timing.
Figures 25 and 26 present Reset 1 and Reset 2, respectively. Figures 27 and 28 present the bus
hold entering and bus hold leaving, respectively. Table 92 presents the reset and bus hold
timing.
Figure 29 presents the synchronous serial interface. Table 93 presents the synchronous serial
interface timing.
Table 80. AC Characteristics Over Commercial Operating Ranges (40 MHz)
No. Name
Description
Min
Max
General Timing Requirements
1 tDVCL Data in Setup
10
–
2 tCLDX Data in Hold
0
–
General Timing Responses
3 tCHSV Status Active Delay
0
6
4 tCLSH Status Inactive Delay
0
6
5 tCLAV
ad Address Valid Delay
0
12
6 tCLAX
Address Hold
0
12
8 tCHDX Status Hold Time
0
–
9 tCHLH ale Active Delay
0
8
10 tLHLL
ale Width
tCLCH-5
–
11 tCHLL
ale Inactive Delay
0
8
12 tAVLL
ad Address Valid to ale Low
tCLCH
–
13 tLLAX
ad Address Hold from ale Inactive
tCHCL
–
14 tAVCH ad Address Valid to Clock High
0
–
15 tCLAZ
ad Address Float Delay
0
12
16 tCLCSV mcs_n/pcs_n Inactive Delay
0
12
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive
tCLCH
–
18 tCHCSX mcs_n/pcs_n Inactive Delay
0
12
19 tDXDL den_n Inactive to dt/r_n Low
0
–
20 tCVCTV Control Active Delay 1
0
10
21 tCVDEX den_n Inactive Delay
0
0
22 tCHCTV Control Active Delay 2
0
10
23 tLHAV
ale High to Address Valid
7.5
–
80 tCLCLX lcs_n Inactive Delay
0
9
81 tCLCSL lcs_n Active Delay
0
9
82 tCLRF
clkouta High to rfsh_n Invalid
0
12
84 tLRLL
lcs_n Precharge Pulse Width
tCLCL + tCLCH –
®
IA211050831-19
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