IA186EM_11 Datasheet, PDF (48/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Note: It is not recommended that multiple chip-select signals be asserted for
the same physical address, although it may be inescapable in certain
systems. If this is the case, then all overlapping chip-selects must have the
same external ready configuration and the same number of wait states to be
inserted into access cycles.
Internal signals are employed to access the peripheral control block (PCB) and these signals
serve as chip selects that are configured with no wait states and no external ready. Therefore, the
PCB can be programmed with addresses that overlap external chip selects only if these chip
selects are configured in the same manner.
Note: Caution is advised in the use of the DA bit in the LMCS or UMCS
registers when overlapping an additional chip select with either the lcs_n or
ucs_n. Setting the DA bit to 1 prevents the address from being driven onto
the AD bus for all accesses for which the respective chip select is active,
including those for which multiple selects are active.
The mcs_n and pcs_n pins are dual-purpose pins, either as chip selects or PIO inputs or outputs.
However, the respective ready- and wait-state configurations for their chip-select function will
be in effect regardless of the function for which these two pins are programmed. This requires
that even if these pins are configured as PIO and enabled (by writing to the MMCS and MPCS
registers for the mcs_n chip selects and to the PACS and MPCS registers for the pcs_n chip
selects), the ready- and wait-state settings for them must agree with those for any overlapping
chip selects as though they were configured as chip selects.
Although pcs4_n is not available as an external pin, it has ready- and wait-state logic and must
follow the rules for overlapping chip-selects. Conversely, pins pcs6_n and pcs5_n have ready-
and wait-state logic that is disabled when configured as address bits a2 and a1, respectively.
Note: If chip-select configuration rules are not followed, the processor may
hang with the appearance of waiting for a ready signal even in a system
where ready (ardy or srdy) is always set to 1.
4.11 Upper Memory Chip Select
The ucs_n chip select is for the top of memory. On reset, the microcontroller begins fetching
and executing instructions at memory location FFFF0h. As a result, upper memory is usually
used for instruction memory. To this end, ucs_n is active on reset and has a memory range of
64 Kbytes (F0000h to FFFFFh) by default, along with external ready required and 3 wait states
automatically inserted. The lower boundary of ucs_n is programmable to provide ranges of 64 to
512 Kbytes.
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