IA186EM_11 Datasheet, PDF (69/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
1-Mbyte address space. These chip selects may also be configured to access the 64-Kbyte
I/O space.
Programming the Peripheral Chip Selects uses the Peripheral Chip Select (PACS) and the pcs_n
and mcs_n Auxiliary (MPCS) registers. The PACS register establishes the base address,
configures the ready mode, and determines the number of wait states for the pcs3_n–pcs0_n
outputs.
The MPCS register configures the pcs6_n–pcs5_n pins to be either chip selects or address pins
a1 and a2. When these pins are configured as chip selects, the MPCS register determines the
ready and wait states for these output pins and whether they are active during memory or I/O bus
cycles. These pins are activated as chip selects by writing to the two registers (PACS and
MPCS). They are not active on reset. To configure and activate them as address pins, it is
necessary to write to both the PACS and MPCS registers. Pins pcs6_n–pcs5_n can be
configured for 0 to 3 wait states and pcs3_n–pcs0_n can be programmed for 0 to 15 wait states.
The value of the PACS register is undefined at reset (see Table 32).
Table 32. Peripheral Chip Select Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BA19–BA11
Reserved R3 R2 R1–R0
Bits [15–7]—BA19–BA11 → Base Address bits correspond to Bits [19–11] of the 20-bit
programmable base address of the peripheral chip select block and determine the base
address. Because I/O addresses are only 16 bits wide, if the pcs_n chip selects are
mapped to I/O space, these bits must be set to 0000b. The pcs address ranges are shown
below.
Address Ranges of pcs Chip Selects
Range
pcs_n Line
Low
High
pcs0_n
Base Address
Base Address + 255
pcs1_n
Base Address + 256 Base Address + 511
pcs2_n
Base Address + 512 Base Address + 767
pcs3_n
Base Address + 768 Base Address + 1023
Reserved
NA
NA
pcs5_n
Base Address + 1280 Base Address
pcs6_n
Base Address + 1536 Base Address
Bits [6–4]—Reserved → Set to 1.
Bit [3]—R3 → Wait State Value. See pcs3_n–pcs0_n Wait-State Encoding shown below.
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