IA186EM_11 Datasheet, PDF (115/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Table 86. PSRAM Write Cycle Timing
No. Name
Comment
General Timing Requirements
1 tDVCL Data in Setup
2 tCLDX Data in Hold
General Timing Responses
5 tCLAV ad Address Valid Delay
7 tCLDV Data Valid Delay
8 tCHDX Status Hold Time
9 tCHLH ale Active Delay
10 tLHLL ale Width
11 tCHLL ale Inactive Delay
20 tCVCTV Control Active Delay 1
23 tLHAV ale High to Address Valid
80 tCLCLX lcs_n Inactive Delay
81 tCLCSL lcs_n Active Delay
84 tLRLL lcs_n Precharge Pulse Width
Write Cycle Timing Responses
30 tCLDOX Data Hold Time
31 tCVCTX Control Inactive Delay
32 tWLWH wr_n Pulse Width
33 tWHLH wr_n Inactive to ale High
34 tWHDX Data Hold after wr_n
65 tAVWL a Address Valid to wr_n Low
68 tCHAV clkouta High to a Address Valid
87 tAVBL a Address Valid to whb_n/wlb_n Low
Min^a
10
0
0
0
0
0
tCLCH-5
NULL
0
7.5
0
0
tCLCL+ tCLCH
0
0
2tCLCL
tCLCH
tCLCL
tCLCL+ tCHCL
0
tCHCL -1.5
Max^a
–
–
12
12
–
8
–
NULL
10
–
9
9
–
–
10
–
–
–
–
8
–
a_{In nanoseconds.}
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