IA186EM_11 Datasheet, PDF (81/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Bits [11–6]—Reserved → Set to 0.
Bit [5]—MC Maximum Count → When the timer reaches its maximum count, this bit is
set to 1 regardless of the interrupt enable bit. This bit is also set every time Maxcount
Compare Register A or B is reached when in dual maxcount mode. If preferred, this bit
may be used by software polling rather than by interrupts to monitor timer status.
Bit [4]—RTG Retrigger Bit → This pin controls the timer function of the timer input pin.
When set to 1, the count is reset by a 0 to 1 transition on timrin0 or tmrin1. When 0, a
high input on tmrin0 or tmrin1 enables the count and a 1 holds the timer value. This bit
is ignored if the external clocking (EXT = 1) bit is set.
Bit [3]—P Prescaler Bit → P is ignored if external clocking is enabled (EXT = 1). Timer
2 prescales the timer when P is set to 1. Otherwise, the timer is incremented on every
fourth clkout cycle.
Bit [2]—EXT External Clock Bit → This bit determines whether an external or internal
clock is used. If EXT is 1, an external clock is used. If 0, an internal is used.
Bit [1]—ALT Alternate Compare Bit → If set to 1, the timer will count to Maxcount
Compare A, reset the count register to 0, count to Maxcount Compare B, reset the count
register to 0, and begin again at Maxcount Compare A. If 0, it will count to Maxcount
Compare A, reset the count register to 0, and begin again at Maxcount Compare A.
Maxcount Compare B is not used in this case.
Bit [0]—CONT Continuous Mode Bit → When set to 1, the timer runs continuously.
When 0, the timer stops after each count run and EN will be cleared. If CONT = 1 and
ALT = 1, the respective timer counts to the Maxcount Compare A value and resets, then
commences counting to Maxcount Compare B value, resets, and stops counting.
5.1.28 T2CON (066h)
Timer 2 Mode and CONtrol Register. This register controls the operation of Timer 2. The value
of the T2CON register is 0000h at reset (see Table 50).
Table 50. Timer 2 Mode and Control Registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN INHn INT
Reserved
MC Reserved CONT
Bit [15]—EN Enable Bit → The timer is enabled when the EN bit is 1. The timer count
is inhibited when the EN bit is 0. Setting this bit to 1 by writing to the T2CON register
requires that the INH bit be set to 1 during the same write. This bit is write-only and can
only be written if the INHn bit (Bit [14]) is set to 1 in the same operation.
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