IA186EM_11 Datasheet, PDF (35/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
2.2.21 lcs_n/once0_n—Lower Memory Chip Select (synchronous output with internal
pull-up)/ONCE Mode Request (input)
The lcs_n pin provides an indication that a memory access is occurring to the lower memory
block. The size of the Lower Memory Block and its base address are programmable, with the
size adjustable up to 512 Kbytes. The lcs_n is held high during bus hold.
The once0_n pin (ONCE – ON Circuit Emulation) and its companion pin, once1_n, define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if
both are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE
mode, all pins are tristated and remain so until a subsequent reset. To prevent the
microcontroller from entering ONCE mode inadvertently, this pin has a weak pull-up that is only
present during reset. This pin is not tristated during bus hold.
2.2.22 mcs2_n—mcs0_n (no pio, pio15, pio 14)—Midrange Memory Chip Selects
(synchronous outputs with internal pull-up)
The mcs2_n and mcs0_n pins provide an indication that a memory access is in progress to the
second or third midrange memory block. The size of the Midrange Memory Block and its base
address are programmable. The mcs2_n – mcs0_n are held high during bus hold and have weak
pull-ups that are only present during reset.
2.2.23 mcs3_n/rfsh_n (pio25)—Midrange Memory Chip Select (synchronous output with
internal pull-up)/Automatic Refresh (synchronous output)
The mcs3_n pin provides an indication that a memory access is in progress to the fourth region
of the midrange memory block. The size of the Midrange Memory Block and its base address
are programmable. The mcs3_n is held high during bus hold and has a weak pull-up that is
present only during reset.
The rfsh_n signal is timed for auto refresh to PSRAM or DRAM devices. The refresh pulse is
output only when the PSRAM or DRAM mode bit is set (EDRAM register Bit [15]). This pulse
is of 1.5 clock-pulse duration with the rest of the refresh cycle made up of a deassertion period
such that the overall refresh time is met. This pin is not tristated during a bus hold.
2.2.24 nmi—Nonmaskable Interrupt (synchronous edge-sensitive input)
Unlike int4 – int0, this is the highest priority interrupt signal and cannot be masked. Upon the
assertion of this interrupt (transition from Low to High), program execution is transferred to the
nonmaskable interrupt vector in the interrupt vector table and this interrupt is initiated at the next
instruction boundary. For recognition to be assured, the nmi pin must be held high for at least a
clkouta period so that the transition from low to high is latched and synchronized internally. The
interrupt will begin at the next instruction boundary.
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