IA186EM_11 Datasheet, PDF (108/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Table 83. Read Cycle Timing
No. Name
Description
General Timing Requirements
1 tDVCL Data in Setup
2 tCLDX Data in Hold
General Timing Responses
3 tCHSV Status Active Delay
4 tCLSH Status Inactive Delay
5 tCLAV ad Address Valid Delay
6 tCLAX Address Hold
8 tCHDX Status Hold Time
9 tCHLH ale Active Delay
10 tLHLL ale Width
11 tCHLL ale Inactive Delay
12 tAVLL ad Address Valid to ale Low
13 tLLAX ad Address Hold from ale Inactive
14 tAVCH ad Address Valid to Clock High
15 tCLAZ ad Address Float Delay
16 tCLCSV mcs_n/pcs_n Inactive Delay
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive
18 tCHCSX mcs_n/pcs_n Inactive Delay
19 tDXDL den_n Inactive to dt/r_n Low
20 tCVCTV Control Active Delay 1
21 tCVDEX den_n Inactive Delay
22 tCHCTV Control Active Delay 2
23 tLHAV ale High to Address Valid
Read Cycle Timing Responses
24 tAZRL ad Address Float to rd_n Active
25 tCLRL rd_n Active Delay
26 tRLRH rd_n Pulse Width
27 tCLRH rd_n Inactive Delay
28 tRHLH rd_n Inactive to ale High
29 tRHAV rd_n Inactive to ad Address Active
66 tAVRL a Address Valid to rd_n Low
67 tCHCSV clkouta High to lcs_n/usc_n Valid
68 tCHAV clkouta High to a Address Valid
Min^a
10
0
0
0
0
0
0
0
tCLCH-5
0
tCLCH
tCHCL
0
0
0
tCLCH
0
0
0
0
0
7.5
0
0
tCLCL
0
tCLCH
tCLCL
tCLCL + tCHCL
0
0
Max^a
–
–
6
6
12
12
–
8
–
8
–
–
–
12
12
–
12
–
10
9
10
–
–
10
–
10
–
–
–
9
8
a_{In nanoseconds.}
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