IA186EM_11 Datasheet, PDF (40/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
2.2.44 ucs_n/once1_n—Upper Memory Chip Select (synchronous output)/ONCE Mode
Request 1 (input with internal pull-up)
The ucs_n pin provides an indication that a memory access is in progress to the upper memory
block. The size of the Upper Memory Block and its base address are programmable, with the
size adjustable to 512 Kbytes. The ucs_n is held high during bus hold.
After power-on-reset, ucs_n is active low and program execution begins at FFFF0h. Its default
configuration is a 64-Kbyte memory range from F0000h to FFFFFh.
The once0_n pin (ONCE – ON Circuit Emulation) and its companion pin, once1_n, define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if
both are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE
mode, all pins are tristated and remain so until a subsequent reset. To prevent the
microcontroller from entering ONCE mode inadvertently, this pin has a weak pull-up that is only
present during reset. This pin is not tristated during bus hold.
2.2.45 uzi_n/pio26—Upper Zero Indicate (synchronous output)
This pin allows the designer to determine if an access to the interrupt vector table is in progress
by ORing it with Bits [15–10] of the address and data bus (ad15–ad10 on the IA186EM and
ao15–ao10 on the IA188EM). The uzi_n is the logical OR of the inverted a19–a16 bits. It
asserts in the first period of a bus cycle and is held throughout the cycle.
At reset, uzi_n should be pulled high or allowed to float. If this pin is pulled low at reset, the
microcontroller enters a reserved clock test mode.
2.2.46 v_cc—Power Supply (input)
These pins supply power (+5V +10%) to the microcontroller.
2.2.47 whb_n (IA186EM)—Write High Byte (synchronous output with tristate)
The whb_n and wlb_n pins indicate to the system which bytes of the data bus (upper, lower, or
both) are taking part in a write cycle. The whb_n is asserted with ad15–ad8 and is the logical
OR of bhe_n and wr_n. It is tristated during reset.
2.2.48 wlb_n/wb_n—Write Low Byte (IA186EM) (synchronous output with tristate)/Write
Byte (IA188EM) (synchronous output with tristate)
The wlb_n and whb_n pins indicate to the system which bytes of the data bus (upper, lower, or
both) are taking part in a write cycle. The wlb_n is asserted with ad7–ad0 and is the logical OR
of ad0 and wr_n. It is tristated during reset.
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