IA186EM_11 Datasheet, PDF (68/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Unlike the ucs_n and lcs_n chip selects, the mcs3_n–mcs0_n outputs assert with the multiplexed
ad address bus (ad15–ad0 for the IA186EM and ao15–ao8 and ad7–ad0 for the IA188EM),
rather than the earlier timing of the a19–a0 bus. If the a19–a0 bus is used for address selection,
the timing is delayed for a half cycle later than that for ucs_n and lcs_n. The value is undefined
at reset (see Table 31).
Table 31. Midrange Memory Chip Select Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BA19–BA13
Reserved
R2 R1–R0
Bits [15–9]—BA19–BA13 Base Address → The value of the this pin determines the base
address of the memory block that is addressed by the mcs_n chip select pins. These bits
correspond to a19–a13 of the 20-bit memory address. The remaining bits a12–a0 of the
base address are always 0.
– The base address may be any integer multiple of the size of the memory clock
selected in the MPCS register. For example, if the midrange block is 32 Kbytes, the
block could be located at 20000h or 28000h but not at 24000h.
– If the lcs_n chip select is inactive, the base address of the midrange chip selects can
be set to 00000h, because the lcs_n chip select is defined to be 00000h but is unused.
Because the base address must be an integer multiple of the block size, a 512K
MMCS block size can only be used with the lcs_n chip select inactive and the base
address of the midrange chip selects set to 00000h.
Bits [8–3]—Reserved → Set to 1.
Bit [2]—R2 Ready mode → This bit determines the mcs_n chip select ready mode.
When set to 1, an external ready is ignored. When 0, it is necessary. In each case, the
number of wait states inserted in an access is determined by the value of the R1 and R0
bits.
Bits [1–0]—R1–R0 → Wait-State Value. The value of these bits determines the number
of wait states inserted in an access. Up to three wait states can be inserted (R1–R0 = 00b
to 11b).
5.1.16 PACS (0a4h)
PeripherAl Chip Select Register. These Peripheral Chip Selects are asserted over a 256-byte
range with the same timing as the ad address bus. There are six chip selects, pcs6_n–pcs5_n and
pcs3_n–pcs0_n, that are used in either the user-locatable memory or I/O blocks. The pcs4_n
chip select is not implemented in the IA186EM or IA188EM. Excluding the areas used by the
ucs_n, lcs_n, and mcs_n chip selects, the memory block can be located anywhere within the
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