IA186EM_11 Datasheet, PDF (71/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
LMCS Block-Size Programming Values
Memory Ending
Block Size Address UB2–UB0
64K
0FFFFh 000b
128K 1FFFFh 001b
256K 3FFFFh 011b
512K 7FFFFh 111b
Bits [11–8]—Reserved → Set to 1.
Bit [7]—DA → Disable Address. When set to 1, the address bus is disabled, providing
some measure of power saving. When 0, the address is driven onto the address bus
ad15–ad0 during the address phase of a bus cycle. This bit is set to 0 at reset.
– If bhe_n/aden_n (IA186EM) is held at 0 during the rising edge of res_n, the address
bus is always driven, regardless of the setting of DA.
Bit [6]—PSE → PSRAM Mode Enable. When set to 1, PSRAM support for the lcs_n
chip select memory space is enabled. The EDRAM, MDRAM, and CDRAM RCU
registers must be configured for auto refresh before PSRAM support is enabled. Setting
the enable bit (EN) in the enable RCU register (EDRAM, offset e4h) configures the
mcs3_n/rfsh_n as rfsh_n.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 → Ready Mode. When set to 1, the external ready is ignored. When 0, it is
required. The value of R1–R0 bits determines the number of wait states inserted.
Bits [1–0]—R1–R0 → Wait-State Value. The value of these bits determines the number
of wait states inserted into an access to the lcs_n memory area. This number ranges from
0 to 3 (R1–R0 = 00b to 11b).
5.1.18 UMCS (0a0h)
The Upper Memory Chip Select Register configures the UMCS pin, used for the top of memory.
On reset, the first fetch takes place at memory location FFFF0h and thus this area of memory is
usually used for instruction memory. The ucs_n defaults to an active state at reset with a
memory range of 64 Kbytes (F0000h to FFFFFh), external ready required, and three wait states
automatically inserted. The upper end of the memory range always ends at FFFFFh. The lower
end of this upper memory range is programmable. The value of the UMCS register is F03Bh at
reset (see Table 34).
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