IA186EM_11 Datasheet, PDF (49/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
4.12 Low Memory Chip Select
The lcs_n chip-select is for lower memory. As the interrupt vector table is at the bottom of
memory beginning at 00000h, this pin us usually used for control data memory. Unlike ucs_n,
this pin is inactive on reset, but can be activated by any read or write to the LMCS register.
4.13 Midrange Memory Chip Selects
There are four midrange chip selects, mcs3_n–mcs0_n, which may be used in a user-located
memory block. With some exceptions, the base address of the memory block may be located
anywhere in the 1-Mbyte memory address space (those used by the ucs_n and lcs_n chip selects,
as well as the pcs6_n, pcs5_n, and pcs3_n–pcs0_n, are excluded). If the pcs_n chip selects are
mapped to I/O space, then the MCS address range can overlap the PCS address range.
Both the Midrange Memory Chip Select (MMCS) register and the MCS and PCS auxiliary
(MPCS) registers are used to program the four midrange chip selects. The MPCS register is used
to configure the block size, whereas the MMCS register configures the base address, the ready
condition, and the wait states of the memory block accessed by the mcs_n pin. The chip selects
(mcs3_n–mcs0_n) are activated by performing a read or write operation of the MMCS and
MPCS registers. The assertion of the MCS outputs occurs with the same timing as the
multiplexed AD address bus (ad15–ad0 on the IA186EM or ao15–ao8 and ad7–ad0 on the
IA188EM). The a19–a0 may be used for address selection, but the timing will be delayed by a
half clock cycle over the timing used for the ucs_n and lcs_n.
4.14 Peripheral Chip Selects
There are six peripheral chip selects (pcs6_n, pcs5_n, and pcs3_n–pcs0_n) that may be used
within a user-defined memory or I/O block. The base address of this user-defined memory block
can be located anywhere within the 1-Mbyte memory address space except for the spaces
associated with the ucs_n, lcs_n, and mcs_n chip selects. Or it may be programmed to the
64 Kbyte I/O space. The pcs4_n is not available.
Both the Peripheral Chip Select (PACS) register and the MCS and PCS Auxiliary register
(MPCS) registers are used to program the six peripheral chip selects pcs6_n, pcs5_n, and
pcs3_n–pcs0_n. The PACS register sets the base address, the ready condition, and the wait
states for the pcs3_n–pcs0_n outputs.
The MPCS register configures pcs6_n and pcs5_n pins as either chip selects or address pins a1
and a2, respectively. When these pins are chip selects, the MPCS register also configures them
as being active during memory or I/O bus cycles and during their ready and wait states.
None of the pcs_n pins are active at reset. Both the Peripheral Chip Select (PACS) register and
the MCS and PCS Auxiliary register (MPCS) registers must be read or written to activate the
pcs_n pins as chip selects.
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