IA186EM_11 Datasheet, PDF (67/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Select Sizes of M6–M0 by Total Block Size
Total
Individual
Block Size Select Size M6–M0
8K
2K
0000001b
16K
4K
0000010b
32K
8K
0000100b
64K
16K
0001000b
128K
32K
0010000b
256K
64K
0100000b
512K
128K 1000000b
Bit [7]—EX Pin Selector → This bit determines whether the pcs6_n–pcs5_n pins are
configured as chip selects or as alternate outputs for a2 and a1. When set to 1,
they are configured as peripheral chip select pins. When 0, they become address bits a1
and a2, respectively.
Bit [6]—MS Memory/I/O Space Selector → This bit determines whether the pcs_n pins
are active during either memory or I/O bus cycles. When set to 1, the outputs are active
for memory bus cycles. When 0, they are active for I/O bus cycles.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 Ready Mode → This bit influences only the pcs6_n–pcs5_n chip selects.
When set to 1, external ready is ignored. When 0, it is required. Values determine the
number of wait states to be inserted.
Bits [1–0]—R1–R0 Wait-State Value → These bits influence only the pcs6_n–pcs5_n
chip selects. Their value determines the number of wait states inserted into an access,
depending on whether it is to the pcs_n memory or I/O area. Up to three wait states can
be inserted (R1–R0 = 00b to 11b).
5.1.15 MMCS (0a6h)
Midrange Memory Chip Select (MMCS) Register. Four chip-select pins, mcs3_n–mcs0_n, are
provided for use within a user-locatable memory block. Excluding the areas associated with the
ucs_n and lcs_n chip selects (and if mapped to memory, the address range of the peripheral chip
selects, pcs6_n–pcs5_n and pcs3_n–pcs0_n), the memory block base address can be located
anywhere within the 1-Mbyte memory address space. If the pcs_n chip selects are mapped to
I/O space, the mcs_n address range can overlap the pcs_n address range.
Two registers program the Midrange Chip Selects. The MMCS register determines the base
address, the ready condition, and wait states of the memory block that are accessed through the
mcs_n pins. The pcs_n and mcs_n auxiliary (MPCS) register configures the block size. On
reset, the mcs3_n–mcs0_n pins are not active. Accessing with a write, both the MMCS and
MPCS registers activate these chip selects.
®
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