IA186EM_11 Datasheet, PDF (98/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Table 79. Synchronous Serial Status Registers
15 14 13 12 11 10 9 8 7 6 5 4 3
2
1
0
Reserved
RE/TE DR/DT PB
Bits [15–3]—Reserved.
Bit [2]—RE/TE Receive/Transmit Error Detect → This bit is set to 1 when a read of the
Synchronous Serial Received register or a write to one of the transmit register is detected
while the interface is busy (PB = 1). This bit is reset to 0 when the SDEN output is not
active (DE1–DE0 in the SSC register are 00h).
Bit [1]—DR/DT Data Receive/Transmit Complete → This bit is set to a 1 when the
transmission of data Bit [7] is completed (SCLK rising edge) during a transmit or receive
operation. This bit is reset by a read of the SSR register, when either the SSD0 or SSD1
register is written, when the SSS register is read (unless the SSI completes an operation
and sets the bit in the same cycle), or when both SDEN0 and SDEN1 become inactive.
Bit [0]—PB SSI Port Busy → This bit indicates that a data transmit or receive is
occurring when it is set to 1. When set to 0, it indicates that the port is ready to transmit
or receive data.
5.2 Reference Documents
Additional information on the operation and programming of the IA186EM/ IA188EM can be
found in the following Advanced Micro Devices (AMD) publications:
Am186 EM and Am188 EM Microcontrollers User’s Manual, February 1997,
Publication 19713.
Am186 EM/EMLV and Am188 EM/EMLV Preliminary Data Sheet, February 1997,
Publication 19168, Rev. E, Amendment 0.
6. AC Specifications
Table 80 presents the AC characteristics over commercial operating ranges (40 MHz). Tables 81
and 82 present the alphabetic and numeric keys to waveform parameters, respectively. Figure 11
presents the read cycle. Figure 12 presents the multiple read cycles. Table 83 presents the read
cycle timing. Figure 13 presents the write cycle. Figure 14 presents the multiple write cycles.
Table 84 presents the write cycle timing.
Figure 15 presents the PSRAM read cycle. Table 85 presents the PSRAM read cycle timing.
Figure 16 presents the PSRAM write cycle. Table 86 presents the PSRAM write cycle timing.
Figure 17 presents the PSRAM refresh cycle. Table 87 presents the PSRAM refresh cycle
timing. Figure 18 presents the interrupt acknowledge cycle. Table 88 presents the interrupt
®
IA211050831-19
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 98 of 146
1-888-824-4184