IA186EM_11 Datasheet, PDF (139/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
7.2.1 Opcode
Opcode parameters and definitions are provided below.
Parameter
/0 - /7
/r
/sr
cb
cd
ib
iw
rw
Definition
The Auxiliary Field in the Operand Address byte specifies an extension (from 000 to 111,
i.e., 0 to 7) to the opcode instead of a register. Thus, the opcode for adding (AND) an
immediate byte to a general byte register or a byte in memory is ―80 /4 ib.‖ This indicates
that the second byte of the opcode is ―mod 100 r/m.‖
The Auxiliary Field in the Operand Address byte specifies a register rather that an opcode
extension. The opcode byte specifies which register, either byte size or word size, is
assigned as in the aux code above.
This byte is placed before the instruction as shown in Section 7.1.7, Segment Override
Prefix.
The byte following the Opcode byte specifies the offset.
The double word following the Opcode byte specifies the offset and is some cases a
segment.
Immediate byte—signed or unsigned determined by the Opcode byte.
Immediate word—signed or unsigned determined by the Opcode byte.
Word register operand as determined by the Opcode byte, aux field.
7.2.2 Flags Affected After Instruction
Flags affected after instruction are shown below.
U Undefined
- Unchanged
R Result-dependent
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