IA186EM_11 Datasheet, PDF (85/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Bits [15–5]—Reserved → Set to 0.
Bit [4]—LTM Level-Triggered Mode → The int4 interrupt may be edge- or level-
triggered, depending on the value of the bit. If LTM is 1, int4 is active high level-
sensitive interrupt. If 0, it is a rising-edge triggered interrupt. The interrupt int4 must
remain active (high) until serviced.
Bit [3]—MSK Mask → The int4 signal can cause an interrupt if the MSK bit is 0. The
int4 signal cannot cause an interrupt if the MSK bit is 1.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the serial port interrupt
in relation to other interrupt signals. The interrupt priority is the lowest at 7 upon reset.
The values of PR2–PR0 are shown in the above table.
5.1.34 I3CON (03eh) and I2CON (03ch) (Master Mode)
INT2/INT3 CONtrol Register. The int2 and int3 are designated as interrupt type 0eh and 0fh,
respectively, and may be configured as the interrupt acknowledge pins inta0_n and inta1_n in
cascade mode. The value of these registers is 000Fh at reset (see Table 56).
Table 56. INT2/INT3 Control Register
15 14 13 12 11 10 9 8 7 6 5 4
3 210
Reserved
LTM MSK PR2–PR0
Bits [15–5]—Reserved → Set to 0.
Bit [4]—LTM Level-Triggered Mode → The int2 or int3 interrupt may be edge- or level-
triggered depending on the value of this bit. If LTM is 1, int2 or int3 is an active high
level-sensitive interrupt. If 0, int2 or int3 is a rising-edge-triggered interrupt. The
interrupt int2 or int3 must remain active (high) until acknowledged.
Bit [3]—MSK Mask → The int2 or int3 signal can cause an interrupt if the MSK bit is 0.
The int2 or int3 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask
Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the serial port interrupt
int2 or int3 in relation to other interrupt signals. The interrupt priority is the lowest at 7
at reset. The values of PR2–PR0 are shown above.
5.1.35 I1CON (03ah) and I0CON (038h) (Master Mode)
INT0/INT1 CONtrol Register. The int0 and int1 are designated as interrupt type 0ch and 0dh,
respectively, and may be configured as the interrupt acknowledge pins inta0 and inta1 in cascade
mode. The value of these registers is 000Fh at reset (see Table 57).
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