IA186EM_11 Datasheet, PDF (82/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Bit [14]—INHn Inhibit Bit → Gates the setting of the enable (EN) bit. This bit must be
set to 1 in the same write operation that sets the enable (EN) bit. This bit always reads 0.
Bit [13]—INT Interrupt Bit → An interrupt request is generated, by setting the INT bit to
1, when the Count register reaches its maximum, MC = 1.
Bits [12–6]—Reserved → Set to 0.
Bit [5]—MC Maximum Count → When the timer reaches its maximum count, this bit is
set to 1, regardless of the interrupt enable bit. If preferred, this bit may be used by
software polling rather than by interrupts to monitor timer status.
Bits [4–1]—Reserved → Set to 0.
Bit [0]—CONT Continuous Mode Bit → The timer will run continuously when this bit is
set to 1. The timer will stop after each count run and EN will be cleared if this bit is set
to 0.
5.1.29 T2COMPA (062h), T1COMPB (05ch), T1COMPA (05ah), T0COMPB (054h), and
T0COMPA (052h)
Timer Maxcount COMpare Registers. These registers contain the maximum count value that is
compared to the respective count register. Timer 0 and Timer 1 each have two compare
registers.
If Timer 0 and/or Timer 1 is/are configured to count and compare first to Register A and then
Register B, the tmrout0 or tmrout1 signals can be used to generate various duty-cycle wave
forms.
Timer 2 has only one compare register, T2COMPA.
If one of these timer maxcount compare registers is set to 0000h, the respective timer will count
from 0000h to FFFFh before generating an interrupt request. For example, a timer configured in
this manner with a 40-MHz clock will interrupt every 6.5536 mS.
The value of these registers is undefined at reset (see Table 51).
Table 51. Timer Maxcount Compare Registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TC15–TC0
Bits [15–0]—TC15–TC0 Timer Compare Value → The timer will count to the value in
the respective register before resetting the count value to 0.
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