IA186EM_11 Datasheet, PDF (111/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Table 84. Write Cycle Timing
No. Name
General Timing Requirements
Description
1 tDVCL Data in Setup
2 tCLDX Data in Hold
General Timing Responses
3 tCHSV Status Active Delay
4 tCLSH Status Inactive Delay
5 tCLAV ad Address Valid Delay
6 tCLAX Address Hold
7 tCLDV Data Valid Delay
8 tCHDX Status Hold Time
9 tCHLH ale Active Delay
10 tLHLL
ale Width
11 tCHLL ale Inactive Delay
12 tAVLL
ad Address Valid to ale Low
13 tLLAX
ad Address Hold from ale Inactive
14 tAVCH ad Address Valid to Clock High
16 tCLCSV mcs_n/pcs_n Inactive Delay
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive
18 tCHCSX mcs_n/pcs_n Inactive Delay
19 tDXDL den_n Inactive to dt/r_n Low
20 tCVCTV Control Active Delay 1
22 tCHCTV Control Active Delay 2
23 tLHAV ale High to Address Valid
Write Cycle Timing Responses
30 tCLDOX Data Hold Time
31 tCVCTX Control Inactive Delay
32 tWLWH wr_n Pulse Width
33 tWHLH wr_n Inactive to ale High
34 tWHDX Data Hold after wr_n
35 tWHDEX wr_n Inactive to den_n Inactive
65 tAVWL a Address Valid to wr_n Low
67 tCHCSV clkouta High to lcs_n/usc_n Valid
68 tCHAV clkouta High to a Address Valid
87 tAVBL a Address Valid to whb_n/wlb_n Low
a_{In nanoseconds.}
Data Sheet
February 25, 2011
Min^a
Max^a
10
–
0
–
0
6
0
6
0
12
0
12
0
12
0
–
0
8
tCLCH-5
–
0
8
tCLCH
–
tCHCL
–
0
–
0
12
tCLCH
–
0
12
0
–
0
10
0
9
7.5
–
0
–
0
10
2tCLCL
–
tCLCH
–
tCLCL
–
tCLCH
–
tCLCL + tCHCL –
0
9
0
8
tCHCL -1.5
–
®
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