IA186EM_11 Datasheet, PDF (100/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Table 80. AC Characteristics Over Commercial Operating Ranges (40 MHz) (Continued)
No. Name
Description
Read Cycle Timing Responses
24 tAZRL
ad Address Float to rd_n Active
25 tCLRL
rd_n Active Delay
26 tRLRH rd_n Pulse Width
27 tCLRH rd_n Inactive Delay
28 tRHLH rd_n Inactive to ale High
29 tRHAV rd_n Inactive to ad Address Active
30 tCLDOX Data Hold Time
Write Cycle Timing Responses
31 tCVCTX Control Inactive Delay
32 tWLWH wr_n Pulse Width
33 tWHLH wr_n Inactive to ale High
34 tWHDX Data Hold after wr_n
35 tWHDEX wr_n Inactive to den_n Inactive
41 tDSHLH ds_n Inactive to ale Inactive
59 tRHDX rd_n High to Data Hold on ad Bus
65 tAVWL a Address Valid to wr_n Low
66 tAVRL
a Address Valid to rd_n Low
67 tCHCSV clkouta High to lcs_n/usc_n Valid
68 tCHAV clkouta High to a Address Valid
87 tAVBL
a Address Valid to whb_n/wlb_n Low
Refresh Timing Cycle Parameters
79 tCHRFD clkouta High to rfsh_n Valid
82 tCLRF
clkouta High to rfsh_n Invalid
85 tRFCY rfsh_n Cycle Time
86 tLCRF
lcs_n Inactive to rfsh_n Active Delay
clkin Timing
36 tCKIN
x1 Period
37 tCLCK x1 Low Time
38 tCHCK x1 High Time
39 tCKHL x1 Fall Time
40 tCKLH x1 Rise time
clkout Timing
42 tCLCL
clkouta Period
43 tCLCH clkouta Low Time
44 tCHCL clkouta High Time
45 tCH1CH2 clkouta Rise Time
46 tCL2CL1 clkouta Fall Time
61 tLOCK Maximum PLL Lock Time
69 tCICOA x1 to clkouta Skew
70 tCICOB x1 to clkoutb Skew
Min
Max
0
–
0
10
tCLCL
–
0
10
tCLCH
–
tCLCL
–
0
–
0
2tCLCL
tCLCH
tCLCL
tCLCH
tCLCH
0
tCLCL + tCHCL
tCLCL + tCHCL
0
0
tCHCL -1.5
10
–
–
–
–
–
–
–
–
9
8
tCHCL
0
12
0
12
6tCLCL
–
2tCLCL
–
25
66
7.5
–
7.5
–
–
5
–
5
25
–
TCLCL/2
–
TCLCL/2
–
–
3
–
3
–
0.5
–
25
–
35
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