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IA186EM_11 Datasheet, PDF (91/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers | |||
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IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Table 66. In-Service Register (Master Mode)
15 14 13 12 11 10 9 8 7 6 5 4 3 2
1
0
Reserved
SPI WD
I4âI0
D1âD0 Reserved TMR
Bits [15â11]âReserved.
Bit [10]âSPI Serial Port Interrupt Request â This is the serial port 0 interrupt state.
Bit [9]âWD Watchdog Timer Interrupt In-Service Request â This bit is the In-Service
state of the Watchdog Timer.
Bits [8â4]âI4âI0 Interrupt Requests â Setting any of these bits to 1 indicates that the
relevant interrupt has a pending interrupt.
Bits [3â2]âD1âD0 DMA Channel Interrupt In-Service â This bit is the In-Service state
of the respective DMA channel.
Bit [1]âReserved.
Bit [0]âTMR Timer Interrupt Request â This is the timer interrupt state and is the
logical OR of the timer interrupt requests. Setting this bit to 1 indicates that the timer
control unit has a pending interrupt.
5.1.45 INSERV (02ch) (Slave Mode)
This is a read-only register and such a read supplies the status of the interrupt request bits
presented to the interrupt controller.
When an internal interrupt request (D1, D0, TMR2, TMR1, and TMR0) occurs, the respective bit
is set to 1. The internally generated interrupt acknowledge resets these bits. The REQST
register contains 0000h on reset (see Table 67).
Table 67. In-Service Register (Slave Mode)
15 14 13 12 11 10 9 8 7 6 5
4 32
1
0
Reserved
TMR2 TMR1 D1âD0 Reserved TMR0
Bits [15â6]âReserved.
Bit [5]âTMR2 Timer 2 Interrupt In Service â Timer 2 is being serviced when this bit is
set to 1.
Bit [4]âTMR1 Timer 1 Interrupt In Service â Timer 1 is being serviced when this bit is
set to 1.
®
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