IA186EM_11 Datasheet, PDF (113/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Table 85. PSRAM Read Cycle Timing
No. Name
Comment
General Timing Requirements
1 tDVCL Data in Setup
2 tCLDX Data in Hold
General Timing Responses
5 tCLAV ad Address Valid Delay
7 tCLDV Data Valid Delay
8 tCHDX Status Hold Time
9 tCHLH ale Active Delay
10 tLHLL ale Width
11 tCHLL ale Inactive Delay
23 tLHAV ale High to Address Valid
80 tCLCLX lcs_n Inactive Delay
81 tCLCSL lcs_n Active Delay
84 tLRLL lcs_n Precharge Pulse Width
Read Cycle Timing Responses
24 tAZRL ad Address Float to rd_n Active
25 tCLRL rd_n Active Delay
26 tRLRH rd_n Pulse Width
27 tCLRH rd_n Inactive Delay
28 tRHLH rd_n Inactive to ale High
59 tRHDX rd_n High to Data Hold on ad Bus
66 tAVRL a Address Valid to rd_n Low
68 tCHAV clkouta High to a Address Valid
Min^a
10
0
0
0
0
0
tCHCL-5
0
7.5
0
0
tCLCL+ tCLCH
0
0
tCLCL
0
tCLCH
0
tCLCL+ tCHCL
0
Max^a
NLL
–
12
12
–
8
–
8
–
9
9
–
–
10
–
10
–
–
–
8
a_{In nanoseconds.}
Data Sheet
February 25, 2011
®
IA211050831-19
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