IA186EM_11 Datasheet, PDF (33/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
2.2.14 hlda—Bus Hold Acknowledge (synchronous output)
This pin is pulled high to signal the system that the microcontroller has ceded control of the local
bus, in response to a high on the hold signal by an external bus master, after the microcontroller
has completed the current bus cycle. The assertion of hlda is accompanied by the tristating of
den_n, rd_n, wr_n, s2_n–s0_n, ad15–ad0, s6, a19–a0, bhe_n, whb_n, wlb_n, and dt/r_n,
followed by the driving high of the chip selects ucs_n, lcs_n, mcs3_n–mcs0_n, pcs6_n–pcs5_n,
and pcs3_n–pcs0_n. The external bus master releases control of the local bus by the deassertion
of hold that in turn induces the microcontroller to deassert the hlda. The microcontroller can
take control of the bus if necessary (to execute a refresh for example), by deasserting hlda
without the bus master first deasserting hold. This requires that the external bus master be able
to deassert hold to permit the microcontroller to access the bus.
2.2.15 hold—Bus Hold Request (synchronous level-sensitive input)
This pin is pulled high to signal the microcontroller that the system requires control of the local
bus.
The hold latency time (time between the hold and hlda) depends on the current processor activity
when the hold is received. A hold request is second only to a DMA refresh request in priority of
processor activity requests. If a hold request is received at the moment a DMA transfer starts,
the hold latency can be up to 4 bus cycles. (This happens only on the IA186EM when a word
transfer is taking place from an odd to an odd address.) This means that the latency may be 16
clock cycles without wait states. Furthermore, if lock transfers are being performed, then the
latency time is increased during the locked transfer.
2.2.16 int0—Maskable Interrupt Request 0 (asynchronous input)
The int0 pin provides an indication that an interrupt request has occurred, and provided that int0
is not masked, program execution will continue at the location specified by the INT0 vector in
the interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled.
2.2.17 int1/select_n—Maskable Interrupt Request 1/Slave Select (both are asynchronous
inputs)
The int1 pin provides an indication that an interrupt request has occurred, and provided that int1
is not masked, program execution will continue at the location specified by the int1 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled.
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