IA186EM_11 Datasheet, PDF (32/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Holding aden_n high or letting it float during POR passes control of the address function of the
ad bus (ad15–ad0) during LCS and UCS bus cycles from aden_n to the Disable Address (DA) bit
in Low-Memory Chip Select (LMCS) and Upper Memory Chip Select (UMCS) registers. When
the address function is selected, the memory address is placed on the a19–a0 pins.
Holding aden_n low during POR, both the address and data are driven onto the ad bus
independently of the DA bit setting. This pin is normally sampled one clock cycle after the
rising edge of res_n.
2.2.8 clkouta—Clock Output A (synchronous output)
This pin is the internal clock output to the system. Bits [9–8] and Bits [2–0] of the Power-Save
Control register (PDCON) control the output of this pin, which may be tristated, output the
crystal input frequency (x1), or output the power save frequency (internal processor frequency
after divisor). The clkouta can be used as a full-speed clock source in power-save mode. The
AC timing specifications that are clock-related refer to clkouta, which remains active during
reset and hold conditions.
2.2.9 clkoutb—Clock Output B (synchronous output)
This pin is an additional clock output to the system. Bits [11–10] and [2–0] of the Power-Save
Control register (PDCON) control the output of this pin, which may be tristated, output the PLL
frequency, or may output the power-save frequency (internal processor frequency after divisor).
The clkoutb remains active during reset and hold conditions.
2.2.10 den_n/pio5—Data Enable Strobe (synchronous output with tristate)
This pin provides an output enable to an external bus data bus transmitter or receiver. This
signal is asserted during I/O, memory, and interrupt acknowledge processes and is deasserted
when dt/r_n undergoes a change of state. It is tristated for a bus hold or reset.
2.2.11 drq1/pio12–drq0/pio13—DMA Requests (synchronous level-sensitive inputs)
An external device that is ready for DMA channel 1 or 0 to carry out a transfer indicates to the
microcontroller this readiness on these pins. They are level triggered, internally synchronized,
not latched, and must remain asserted until dealt with.
2.2.12 dt/r_n/pio4—Data Transmit or Receive (synchronous output with tristate)
The microcontroller transmits data when dt/r_n is pulled high and receives data when this pin is
pulled low. It floats during a reset or bus hold condition.
2.2.13 gnd—Ground
Six or seven pins, depending on package, connect the microcontroller to the system ground.
®
IA211050831-19
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 32 of 146
1-888-824-4184