IA186EM_11 Datasheet, PDF (50/146 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
The pcs6_n and pcs5_n may be programmed to have 0 to 3 wait states, whereas pcs3_n–pcs0_n
may be programmed to have these and 5, 7, 9, and 15 wait states.
4.15 Refresh Control
The Refresh Control Unit (RCU) generates refresh bus cycles. The RCU generates a memory
read request after a programmable period of time to the bus interface unit.
The ENA bit in the Enable RCU register (EDRAM) enables refresh cycles, operating off the
processor internal clock. If the processor is in power-save mode, the RCU must be reconfigured
for the new clock rate.
If the hlda pin is asserted when a refresh request is initiated (indicating a bus hold condition), the
processor disables the hlda pin to allow a refresh cycle to be performed. The external circuit bus
master must deassert the hold signal for at least one clock period to permit the execution of the
refresh cycle.
4.16 Interrupt Control
Interrupt requests originate from a variety of internal and external sources that are arranged by
the internal interrupt controller in priority order and presented one by one to the processor.
Six external interrupt sources—five maskable (int4–int0) and one nonmaskable (NMI)—are
connected to the processor and six internal interrupt sources (three timers, two DMA channels,
and the asynchronous serial port that are not brought out to external pins).
The five external maskable interrupt request pins can be used as direct interrupt requests.
However, should more interrupts be needed, int3–int0 may be used with the 82C59A-compatible
external interrupt controller. By programming the internal interrupt controller to slave mode, a
82C59A-compatible external interrupt controller can be used as the system master. Interrupt
nesting can be used in all cases that permit interrupts of a higher priority to interrupt those of a
lower priority.
When an interrupt is accepted, other interrupts are disabled, but may be re-enabled by setting the
Interrupt Enable Flag (IF) in the Processor Status Flags register during the Interrupt Service
Routine (ISR). Setting IF permits interrupts of equal or greater priority to interrupt the currently
running ISR.
Further interrupts from the same source will be blocked until the corresponding bit in the
In-Service register (INSERV) is cleared. Special Fully Nested mode (SFNM) is invoked for int0
and int1 by the SFNM bit in the INT0 and INT1 control register, respectively, when this bit is set
to 1. In this mode, a new interrupt may be generated by these sources regardless of the in-service
bit. The following table shows the priorities of the interrupts at POR.
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IA211050831-19
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