MC9RS08KA8RM Datasheet, PDF (99/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Analog-to-Digital Converter (RS08ADC10V1)
7
6
5
4
R COCO
W
AIEN
ADCO
3
2
1
0
ADCH
Reset:
0
0
0
1
1
1
1
1
= Unimplemented or Reserved
Figure 10-3. Status and Control Register (ADCSC1)
Table 10-3. ADCSC1 Register Field Descriptions
Field
Description
7
COCO
Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is
completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE =
1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared
whenever ADCSC1 is written or whenever ADCRL is read.
0 Conversion not completed
1 Conversion completed
6
AIEN
Interrupt Enable — AIEN enables conversion complete interrupts. When COCO becomes set while AIEN is
high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
5
ADCO
Continuous Conversion Enable — ADCO is used to enable continuous conversions.
0 One conversion following a triggered operation¹
1 Continuous conversions initiated following a triggered operation is selected.
4:0
ADCH
Input Channel Select — The ADCH bits form a 5-bit field which selects one of the input channels. The input
channels are detailed in Figure 10-4.
The successive approximation converter subsystem is turned off when the channel select bits are all set to 1.
This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.
Terminating continuous conversions this way prevents an additional, single conversion from being performed. It
is not necessary to set the channel select bits to all 1s to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
1 _{See Table 10-4 for how to specify a hardware or software trigger type (ADTRG).}
ADCH
00000
00001
00010
00011
00100
00101
00110
00111
Figure 10-4. Input Channel Select
Input Select
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADCH
10000
10001
10010
10011
10100
10101
10110
10111
Input Select
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
99