MC9RS08KA8RM Datasheet, PDF (126/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Internal Clock Source (S08ICSV1)
11.3.3 ICS Trim Register (ICSTRM)
7
R
W
POR:
1
Reset:
U
6
5
4
3
TRIM
2
1
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
Figure 11-5. ICS Trim Register (ICSTRM)
Table 11-4. ICS Trim Register Field Descriptions
Field
7:0
TRIM
Description
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect is binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing
the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
11.3.4 ICS Status and Control (ICSSC)
7
R
0
W
POR:
0
Reset:
0
6
5
4
0
0
0
0
0
0
0
0
0
3
2
CLKST
0
0
0
0
1
OSCINIT
0
FTRIM
0
0
0
U
Figure 11-6. ICS Status and Control Register (ICSSC)
Table 11-5. ICS Status and Control Register Field Descriptions
Field
Description
7:4
3-2
CLKST
1
OSCINIT
0
FTRIM
Reserved, must be cleared.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Output of FLL is selected.
01 FLL bypassed, internal reference clock is selected.
10 FLL bypassed, external reference clock is selected.
11 Reserved.
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when ERCLKEN or EREFS is cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
MC9RS08KA8 Series Reference Manual, Rev. 3
126
Freescale Semiconductor