MC9RS08KA8RM Datasheet, PDF (100/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Analog-to-Digital Converter (RS08ADC10V1)
Figure 10-4. Input Channel Select (continued)
ADCH
01000
01001
01010
01011
01100
01101
01110
01111
Input Select
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ADCH
11000
11001
11010
11011
11100
11101
11110
11111
Input Select
AD24
AD25
AD26
AD27
Reserved
V_REFH
V_REFL
Module disabled
10.3.2 Status and Control Register 2 (ADCSC2)
The ADCSC2 register is used to control the compare function, conversion trigger and conversion active
of the ADC module.
7
6
5
4
3
R ADACT
0
ADTRG
ACFE
ACFGT
W
Reset:
0
0
0
0
0
= Unimplemented or Reserved
2
1
0
0
R¹
R¹
0
0
0
1 _{Bits 1 and 0 are reserved bits that must always be written to 0.}
Figure 10-5. Status and Control Register 2 (ADCSC2)
Table 10-4. ADCSC2 Register Field Descriptions
Field
7
ADACT
6
ADTRG
5
ACFE
4
ACFGT
Description
Conversion Active — ADACT indicates that a conversion is in progress. ADACT is set when a conversion is
initiated and cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress
Conversion Trigger Select — ADTRG selects the type of trigger to be used for initiating a conversion.
0 Software trigger selected.(initiates a conversion following a write to ADCSC1).
1 Hardware trigger selected.(initiates a conversion following the assertion of the ADHWT input).
Compare Function Enable — ACFE is used to enable the compare function.
0 Compare function disabled
1 Compare function enabled
Compare Function Greater Than Enable — ACFGT configures the compare function to trigger upon
conversion of the input being monitored.
0 Compare triggered when input is less than compare level
1 Compare triggered when input is greater than or equal to compare level
MC9RS08KA8 Series Reference Manual, Rev. 3
100
Freescale Semiconductor