MC9RS08KA8RM Datasheet, PDF (81/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 8 Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Set Summary (Sheet 3 of 6)
Source
Form
Description
Operation
Effect
on
CCR
ZC
DIR (b0) 00
DIR (b1) 02
DIR (b2) 04
DIR (b3) 06
DIR (b4) 08
BRSET n,opr8a,rel
DIR (b5) 0A
DIR (b6) 0C
DIR (b7) 0E
IX (b0)
00
IX (b1)
02
IX (b2)
04
BRSET n,D[X],rel
Branch if Bit n in Memory
Set
PC ← (PC) + $0003 + rel, if (Mn) = 1
—¦
IX (b3)
IX (b4)
06
08
IX (b5)
0A
IX (b6)
0C
IX (b7)
0E
DIR (b0) 00
BRSET n,X,rel
DIR (b1) 02
DIR (b2) 04
DIR (b3) 06
DIR (b4) 08
DIR (b5) 0A
DIR (b6) 0C
DIR (b7) 0E
BSET n,opr8a
BSET n,D[X]
Set Bit n in Memory
Mn ← 1
DIR (b0) 10
DIR (b1) 12
DIR (b2) 14
DIR (b3) 16
DIR (b4) 18
DIR (b5) 1A
DIR (b6) 1C
DIR (b7) 1E
IX (b0)
10
IX (b1)
12
IX (b2)
14
—
—
IX (b3)
IX (b4)
16
18
IX (b5)
1A
IX (b6)
1C
IX (b7)
1E
DIR (b0) 10
BSET n,X
DIR (b1) 12
DIR (b2) 14
DIR (b3) 16
DIR (b4) 18
DIR (b5) 1A
DIR (b6) 1C
DIR (b7) 1E
dd rr 5
dd rr 5
dd rr 5
dd rr 5
dd rr 5
dd rr 5
dd rr 5
dd rr 5
0E rr 5
0E rr 5
0E rr 5
0E rr 5
0E rr 5
0E rr 5
0E rr 5
0E rr 5
0F rr 5
0F rr 5
0F rr 5
0F rr 5
0F rr 5
0F rr 5
0F rr 5
0F rr 5
dd 5
dd 5
dd 5
dd 5
dd 5
dd 5
dd 5
dd 5
0E 5
0E 5
0E 5
0E 5
0E 5
0E 5
0E 5
0E 5
0F 5
0F 5
0F 5
0F 5
0F 5
0F 5
0F 5
0F 5
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
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