MC9RS08KA8RM Datasheet, PDF (28/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 3 Modes of Operation
The external clock source can also be enabled for the real-time interrupt to allow a wakeup from stop mode
with no external components. Setting the ERCLKEN=1 and EREFSTEN=1 enables the external clock
source when in STOP mode.
To enable ADC in STOP mode, the asynchronous ADC clock and LVD must be enabled by setting LVDE
and LVDSE, otherwise the ADC is in standby.
To enable XOSC to operate with an external reference clock source in STOP mode, LVD must be enabled
by setting LVDE and LVDSE.
3.6.1 Active BDM Enabled in Stop Mode
Entry into active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This
register is described in the Chapter 15, “Development Support.” If ENBDM is set when the CPU executes
a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode so background debug communication is still possible. The voltage regulator does not enter its
low-power standby state. It maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access. They report an error indicating that the MCU is in stop or wait mode. The
BACKGROUND command can be used to wake the MCU from stop and enter active background mode
if the ENBDM bit is set. After active background mode is entered, all background commands are available.
Table 3-3 summarizes the MCU behavior in stop when entry into the active background mode is enabled.
Table 3-3. BDM Enabled Stop Mode Behavior
Mode
CPU
Digital
Peripherals
ICS
ACMP Regulator I/O Pins
RTI
ADC
Stop Standby Standby
On
Optionally
on
on
States held Optionally on Optionally on
3.6.2 LVD Enabled in Stop Mode
The LVD system can generate an interrupt or a reset when the supply voltage drops below the LVD
voltage. The voltage regulator remains active if the LVD is enabled in stop (LVDE and LVDSE bits in
SPMSC1 both set) when the CPU executes a STOP instruction.
Table 3-4 summarizes the behavior of the MCU in stop when LVD is enabled.
Table 3-4. LVD Enabled Stop Mode Behavior
Mode
CPU
Digital
Peripherals
ICS
ACMP Regulator I/O Pins
RTI
ADC¹
Stop Standby
Standby
Optionally Optionally
on
on
1 _{Requires the asynchronous ADC clock to be enabled.}
On
States held Optionally on Optionally on
MC9RS08KA8 Series Reference Manual, Rev. 3
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Freescale Semiconductor