MC9RS08KA8RM Datasheet, PDF (42/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 5 Resets, Interrupts, and General System Control
• Low-voltage detect (LVD)
• Computer operating properly (COP) timer
• Illegal opcode detect (ILOP)
• Illegal address detect (ILAD)
• Background debug forced reset via BDC command BDC_RESET
Each source except the background debug forced reset has an associated bit in the system reset status
register (SRS).
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is used to force a system reset if the application software fails to execute as expected.
To prevent a system reset from the COP timer (when it is enabled), application software must periodically
reset the COP counter. If the application program gets lost and fails to reset the COP counter before it times
out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT, which enables the COP watchdog (see Section 5.8.2,
“System Options Register (SOPT).”). If the COP watchdog is not used in an application, it is disabled by
clearing COPE. The COP counter is reset by writing any value to the address of SRS. This write does not
affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a reset
signal to the COP counter.
There is an associated short and long time-out controlled by COPT in SOPT. Table 5-1 summarizes the
COPT bit control functions. The COP watchdog operates from the 1 kHz clock source and defaults to the
associated long time-out (2⁸ cycles).
Table 5-1. COP Configuration Options
COPT
COP Overflow Count¹
0
2⁵ cycles (32 ms)
1
2⁸ cycles (256 ms)
1 _{Values in this column are based on tRTI ≈ 1 ms. See}
t_RTI in the “MC9RS08KA8 Series Data Sheet,” for
the tolerance value.
Even if the application uses the reset default settings of COPE and COPT, write to the write-once SOPT
registers during reset initialization to lock in the settings so they cannot be changed accidentally if the
application program gets lost. The initial write to SOPT resets the COP counter.
In background debug mode, the COP counter does not increment.
When the MCU enters stop mode, the COP counter is re-initialized to zero upon entry to stop mode. The
COP counter begins from zero as soon as the MCU exits stop mode.
5.5 Interrupts
The MC9RS08KA8 series do not include an interrupt controller with vector table lookup mechanism as
used on the HC08 and HCS08 devices. However, the interrupt sources from modules such as LVD, KBI,
MC9RS08KA8 Series Reference Manual, Rev. 3
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