MC9RS08KA8RM Datasheet, PDF (107/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Analog-to-Digital Converter (RS08ADC10V1)
10.4.1 Clock Select and Divide Control
One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
• The bus clock, equal to the frequency at which the software is executed. This is the default selection
following reset.
• The bus clock divided by 2. For higher bus clock rates, this allows a maximum divide by 16 of the
bus clock.
• ALTCLK, as defined for this MCU (See module section introduction).
• The asynchronous clock (ADACK) – This clock is generated from a clock source within the ADC
module. When selected as the clock source this clock remains active while the MCU is in wait or
stop mode and allows conversions in these modes for lower noise operation.
The selected clock’s frequency must fall within the range specified for ADCK. If the available clocks are
too slow, the ADC will not perform according to specifications. If the available clocks are too fast, the
clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be
divided by 1, 2, 4, or 8.
10.4.2 Input Select and Pin Control
The pin control registers (APCTL3, APCTL2, and APCTL1) disable the I/O port control of the pins used
as analog inputs.When a pin control register bit is set, the following conditions are forced for the associated
MCU pin:
• The output buffer is forced to its high impedance state.
• The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer
disabled.
• The pullup is disabled.
10.4.3 Hardware Trigger
The ADC module enables ADHWT, a selectable asynchronous hardware conversion trigger, when the
ADTRG bit is set. This source is not available on all MCUs. Consult the module introduction for
information on the ADHWT source specific to this MCU.
When ADHWT source is available and hardware trigger is enabled (ADTRG=1), a conversion initiates on
the rising edge of ADHWT. If a conversion is in progress when a rising edge occurs, the rising edge is
ignored. In continuous convert configuration, only the initial rising edge to launch continuous conversions
is observed. The hardware trigger function operates with any of the conversion modes and configurations.
10.4.4 Conversion Control
Conversions can be performed in 10-bit mode or 8-bit mode as determined by the MODE bits. Conversions
can be initiated by either a software or hardware trigger. In addition, the ADC module can be configured
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
107